Senior Layout Designer – High‑Speed SERDES/UCIe

About the role

Our client, a leading multinational semiconductor company, is seeking a Senior Layout Designer to join the SERDES/UCIe product team in Cork City, Ireland. The role provides technical leadership on the PMA custom layout design team, working on cutting‑edge high‑speed interfaces.

Key responsibilities

• Design high‑speed SERDES/UCIe products up to and exceeding 112 Gbps on advanced technology nodes (e.g., 3 nm FinFET CMOS).
• Create high‑quality analog/mixed‑signal layout blocks, collaborating closely with circuit designers.
• Manage the full back‑end flow from floor‑planning through detailed layout and final verification against foundry design rules.
• Lead block‑level to PHY top‑level integration, sign‑off, and clock/power distribution strategies.
• Coordinate with global teams across the US and Europe, aligning technical and schedule requirements.

Required profile

• Minimum 7 years of experience in CMOS SERDES or high‑speed I/O IC layout design.
• Proven expertise in layout of driver, receiver, serializer, deserializer, phase interpolator, low‑jitter PLL, high‑speed clock distribution, bias/bandgap circuits, and voltage regulators.
• Experience delivering complete PHY GDSII with integrated PMA and PCS hierarchies.
• Strong problem‑solving abilities, analog aptitude, and effective communication skills.
• BEng, MEng or PhD in Electrical Engineering or related field.

Required skills

• Cadence Virtuoso and PVS layout tools.
• Design on technology nodes below 40 nm, including 3 nm FinFET.
• High‑speed layout (>10 Gbps) and familiarity with SERDES circuit blocks.
• Analog/Mixed‑Signal custom layout techniques.

What we offer

• Opportunity to work on industry‑leading high‑speed interfaces.
• Collaboration with global engineering teams.
• Hybrid work model with four days onsite in Cork.