Mixed‑Signal Digital Design Engineer – Cork

About the role

The Qualcomm Mixed‑Signal IP (MSIP) Digital Design team in Cork is seeking an experienced digital design engineer to create high‑performance, low‑power mixed‑signal IP blocks for mobile, compute, automotive and AI applications.

Key responsibilities

• Architect, design and implement digital sections of mixed‑signal IPs such as SerDes, DDR, PLL, DAC, ADC and sensors.
• Run the full ASIC design toolchain – lint checking, CDC, DFT, synthesis, functional verification and static timing analysis – to validate and implement designs.
• Collaborate with verification (DV) and physical design (PD) teams to define test plans, verify functionality, fix bugs and support physical implementation.
• Create detailed design specifications, documentation and work with the testing team for silicon bring‑up and debug.

Required profile

• Master’s degree in Electrical Engineering, Computer Engineering or a related field.
• 5+ years of ASIC digital design experience, including micro‑architecture definition and RTL coding.
• Hands‑on experience with front‑end ASIC tools such as Design Compiler, Fusion Compiler, Modelsim, VCS, Spyglass and PrimeTime.

Required skills

• ASIC digital design flow: micro‑architecture, RTL coding, front‑end implementation.
• Proficiency with ASIC toolchain (lint, CDC, DFT, synthesis, functional verification, STA).
• Scripting languages Python and Perl.
• Knowledge of low‑power digital design, DSP techniques and mixed‑signal IP blocks (SerDes, DDR PHY, PLL/DLL, DAC/ADC).

What we offer

• Competitive salary, stock options and performance‑related bonus.
• Maternity/Paternity leave, employee stock purchase scheme and matching pension.
• Education assistance, relocation and immigration support.
• Life, medical, income and travel insurance; subsidised well‑being memberships; bicycle purchase scheme; employee clubs.