ASIC Design/Verification Architect

About the role

Synopsys is seeking an experienced ASIC Digital Verification Engineer to lead the verification of high‑performance Interface IP protocols. You will work independently on complex challenges, mentor junior engineers, and collaborate closely with design and architecture teams to ensure robust, reliable silicon.

Key responsibilities

• Design, implement, and optimize verification environments for Interface IP protocols.
• Create, execute, and track detailed test plans for complex ASIC designs.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to identify and fix bugs.
• Perform functional coverage analysis and drive coverage closure.
• Mentor junior verification engineers on best practices and methodologies.

Required profile

• Detail‑oriented with a strong analytical mindset.
• Excellent communicator able to convey complex technical concepts.
• Proven ability to work independently and lead verification efforts.
• Commitment to continuous learning and improvement.

Required skills

• SystemVerilog, SVA, UVM methodologies.
• Experience with Interface IP protocols such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Familiarity with ASIC flow from RTL design through synthesis.
• Simulation tools experience (VCS, ModelSim or similar).
• Functional coverage analysis and verification IP development.