Physical Design Engineer – Advanced SoC Implementation

About the role

We are seeking a talented Physical Design Engineer to join our global implementation team in Cork, Ireland. You will own the end‑to‑end physical implementation of cutting‑edge System‑on‑Chip (SoC) projects using advanced technology nodes and drive innovative Power‑Performance‑Area (PPA) solutions.

Key responsibilities

• Execute the full physical implementation flow from floorplan through GDSII for complex, high‑speed designs with aggressive PPA targets.
• Research and develop new methodologies, flows and automation scripts (Perl, Tcl) to improve PPA in 10nm and smaller nodes.
• Perform statistical analyses and data‑driven optimisation of timing, congestion and power, identifying critical improvement areas.
• Collaborate with RTL, CAD and other cross‑functional teams to align on design intent and PPA strategies.
• Stay up‑to‑date with industry trends and best practices in physical design.

Required profile

• Hands‑on experience in physical design of ASIC/SoC, covering netlist to GDSII.
• Strong knowledge of floorplanning, placement, clock‑tree synthesis, routing and optimisation.
• Proficiency with static timing analysis and timing‑closure techniques.
• Good understanding of power analysis, power integrity and physical verification (DRC/LVS).
• Excellent communication skills and ability to work in a global, collaborative environment.

Required skills

• Perl scripting
• Tcl scripting
• Floorplanning
• Placement
• Clock‑Tree Synthesis (CTS)
• Routing
• Static Timing Analysis (STA)
• Power analysis and Power Integrity (PI)
• Design Rule Check (DRC) and Layout Versus Schematic (LVS)