Senior Layout Designer – High‑Speed SERDES/UCIe

About the role

Our client, a leading multinational semiconductor company, is seeking a Senior AMS Layout Design Engineer to join the SERDES/UCIe product team in Cork, Ireland. The role involves technical leadership on the PMA custom layout design team, working on high‑speed SERDES products up to and beyond 112 Gbps.

Key responsibilities

• Lead the design of high‑speed SERDES/UCIe layouts on advanced nodes (e.g., 3 nm FinFET CMOS).
• Produce high‑quality analog/mixed‑signal block layouts and ensure compliance with foundry design rules.
• Manage the full back‑end flow from floor planning through detailed layout and final verification.
• Coordinate block‑level to PHY top‑level integration and sign‑off activities.
• Collaborate with global teams across the US and Europe, aligning technical and schedule requirements.

Required profile

• Minimum 7 years of experience in CMOS SERDES or high‑speed I/O IC layout design.
• Strong background in designing driver, receiver, serializer, deserializer, phase interpolator, low‑jitter PLL, high‑speed clock distribution, bias/bandgap, and voltage regulator blocks.
• Proven ability to deliver high‑speed, high‑accuracy cells and complete PHY GDSII with optimized clock and power distribution.
• Excellent problem‑solving, analog aptitude, and communication skills.

Required skills

• Cadence Virtuoso and related layout tools.
• Design experience at >10 Gbps and in <40 nm technologies.
• Knowledge of SERDES circuit blocks and high‑speed I/O design.
• Collaboration with Cadence R&D (Virtuoso, PVS) for tool development.